A new extended single-switch high gain DC–DC boost converter for renewable energy applications

High-gain DC/DC converters are considered one of the most important components of green energy systems. Large numbers of these converters are used for increasing the voltage gain by using an extreme duty cycle. However, it increases losses and the cost, degrades the system performance, and hence obtains a low efficiency. In this article, a new design of a high-gain DC/DC boost converter is proposed. This converter has the potential to be used in low input voltage applications that need a high voltage gain such as systems powered by solar photovoltaic panels and fuel cells. The new topology is characterized by its simplicity of operation, high voltage gain, better efficiency, continuity of the input current, reduced number of inductors and capacitors, and can be extended to get higher gains. The converter structure, principle of operation, and design consideration of inductors and capacitors are presented in detail. Derivation of power losses and efficiency is presented. A laboratory prototype is implemented, and various experimental tests are given. The achievement of the suggested design is confirmed and compared with other recent high-gain converters.


The proposed converter and its steady-state investigation
Circuit description and modes of operation. The offered multi-cells DC/DC boost converter is shown in Fig. 1. To understand the operation of the proposed DC-DC boost converter, the circuit with two cells (n = 2) shown in Fig. 2 is analyzed. Each cell contains two passive elements (one inductor and one capacitor), and one diode.
The proposed circuit composes of one active power switch, four diodes, and five passive components. Under assumptions of the ideal power switch and diodes, and pure inductive and capacitive elements, steady state analysis of the two operation modes is discussed. The key waveforms of the two cells of the suggested converter are displayed in Fig. 3. Figure 4 shows the equivalent circuit during mode 1. As obvious SW, D 1 , D 2 , and D 3 are ON, and D o is OFF. The currents (i L1 , i L2 ) of the inductors (L 1 and L 2 ) increase linearly. The inductor's voltage opposes the input dc voltage V in . The capacitors C 1 and C 2 charge with a voltage nearly the same as V in . The saved energy in the capacitor C o supplies the load. The equations of mode 1 can be obtained from Fig. 4b by applying KVL and KCL as follow:

Mode 1 (0 ≤ t ≤ DT).
The supply current during the switching-on period (i s-on ) is given by; www.nature.com/scientificreports/ Mode 2 (DT ≤ t ≤ T). Figure 5 displays the equivalent circuit during mode 2. It is noted that SW, D 1 , D 2 , and D 3 are OFF, and D o is ON. The inductors' voltages V L1 and V L2 are inverted, and the saved energy in the passive components L 1 , L 2 , C 1, and C 2 is transmitted to the load and C o . The equations of mode 2 can be obtained from Fig. 5b by applying KVL and KCL as follow: The supply current during the switching-off period (i s-off ) is given by; Voltage gain derivation and voltage stresses across the switch, diodes, and capacitors. The ripple of the inductor current i L1 during the switching-on interval is: where D is the duty ratio. The ripple of the inductor current i L2 during the switching-on interval is:   www.nature.com/scientificreports/   www.nature.com/scientificreports/ The ripple of the inductor current i L1 during the switching-off interval is: The ripple of the inductor current i L2 during this mode is: By using the volt-sec balance through the inductors L 1 and L 2 , and from Eqs. (5) and (7); Also, Eqs. (6) and (8) yield; By solving Eqs. (9) or (10), the voltage gain can be found as follow: For steady-state operation, the charge on capacitors C 1 and C 2 should not change; and If each of the inductances L 1 and L 2 is large enough, I L1 is nearly equal to its average current I L1 and also, I L2 is nearly equal to its average current I L2 .
For L 1 = L 2 ; Then, from Eq. (4), we obtain Also, by substituting from Eqs. (12), (13), and (14) into Eq. (2), one can obtain: The average supply current can be given as:   This equation can be written as; where G 2 is the voltage gain at number of cells (n) = 2. For n = 3; This equation can be written as: where G 3 is the voltage gain at number of cells (n) = 3.
To generalize the formula based on number of cells (n), the voltage gain can be obtained according to the following formula for n ≥ 1. and the average supply current for any number of cells can be given as following: The voltage gain of the proposed converter at different number of cells (n = 1, 2, and 3) is displayed in Fig. 6. It is obvious that the voltage gain has a higher value in comparison to the conventional DC-DC boost converter. Moreover, the proposed converter can be extended to get higher voltage gains by increasing the cascading additional cells.
Also, the voltage stresses across the switch, diodes, and capacitors for any number of cells can be expressed as: www.nature.com/scientificreports/ Design consideration. The design of inductors and capacitors is considered an important issue to guarantee the operation of the suggested circuit in CCM. Therefore, this part is presented to describe the design of these passive elements.
Inductor design. During Mode 1, the voltage across the inductor is provided by: The voltage across the inductor is the same as the input voltage. The inductance is defined by: where %r i is the percent inductor current ripple allowed. The average value of the inductor current I L can be obtained from Eq. (18), then, substituting into Eq. (33), one obtains: where R L is the load value. Then, the inductance value for any number of cells can be given from the following equation, Capacitor design. The current flowing through the capacitor C 1 in 0 ≤ t ≤ DT period can be obtained from Eqs. (12) and (15) as ((1-D)/D)I L . Then, the capacitance value C 1 can be derived as: where %r v is the percent capacitor voltage ripple allowed in C 1 . By substituting from Eq. (18) into Eq. (36), the capacitance value C 1 can be obtained. In the same way, the capacitance value C 2 can be derived. Hence, For any number of cells, the capacitance value of C 1 and C 2 can be given from the following relation: The capacitor C o is charged in the period DT ≤ t ≤ T, hence, For any number of cells, the capacitance value of C o can be given from the following relation,

Power losses and efficiency
The power losses of the two-cell for the proposed topology are estimated by calculating the switching losses and conduction losses. The power loss of each component is determined, then, the converter power losses can be investigated by summing all these parts. Also, the converter efficiency can be determined based on the power losses. The converter model with the parasitic elements is displayed in Fig. 7.
For the computation of conduction losses in the converter, all diodes are considered with cut in voltages V D1 , V D2 , V D3 , and V Do . Also, the internal resistances are r D1 , r D2 , r D3 , and r Do . Each inductor L 1 and L 2 has a lumped DC resistance r L1 and r L2 , respectively, and each capacitor C 1 , C 2 and C o has an equivalent series resistance r C1 , r C2 , and r Co , respectively. Both conduction and switching losses are considered for the main switch with on-state resistance occupied as r sw .
The power switch losses. The practical power switch has conduction and switching losses. The switching loss is the sum of the conduction and switching losses and it can be written as: where the conduction loss of SW can be stated as: The switch current can be obtained from Mode 1 and Eq. (16), then the rms value of the switch current can be established as: Substituting from (44) into (43), then the power conduction loss can be determined by: The switching loss (P loss-switching ) of the power switch SW can be determined by: www.nature.com/scientificreports/ where t rt and t ft is the rise time and fall time of the switch, respectively. The average current of the switch current can be found as: Substituting from (19) and (47) into (46), then the power switching loss can be determined by: Then the switching loss of SW can be investigated by: The diodes losses. The diodes are supposed to have the same cut in voltages and equivalent series resist- The total diodes losses can be stated as: where, the power loss of each diode can be determined by; Then, the total power loss in the diodes can be determined by substituting from (51), (52), (53), and (54) into (50) as: (46) P loss−switching(SW) = P loss−switching(SW)−on + P loss−switching(SW)−off www.nature.com/scientificreports/ The capacitors losses. There are three capacitors are shown in the proposed topology. The total power loss due to the capacitors is given by: The three capacitors are assumed to has the same equivalent series resistance, r C1 = r C2 = r Co = r C .
The rms value of current through the capacitors and the power loss of each capacitor can be estimated using the expressions: Then, Substituting from (58) into (56), the total power loss due to the capacitors can be given by: The inductors losses. The inductors loss can be expressed as: Assuming the inductors have the same internal resistance r L1 = r L2 = r L and have the same rms value of the inductor currents i L1rms = i L2rms = i Lrms . Then, the inductors losses can be determined as: Using (18), the rms value of the inductor current can be established, then the total power loss in the inductors can be expressed as; Substituting from Eqs. (49), (55), (59), and (61) into the below equation, the total converter loss can be obtained.
The expression for total losses is as follows: where (55) P loss−total(Diodes) = (62) P loss−total = P loss−total(Switches) + P loss−total(Diodes) + P loss−total(Capacitors) + P loss−total(Inductors) www.nature.com/scientificreports/ Finally, the efficiency (ɳ) of the suggested topology can be determined as: where, P o is the output power. Substituting from (63) into (65), the proposed converter efficiency (ɳ) can be defined as:

Experimental results
To authorize the efficacy of the proposed DC-DC boost converter, a prototype has been built in the laboratory. The parameters of the suggested converter are given in Table 1. A photograph of the experimental setup system is shown in Fig. 8, and a schematic drawing for the test system is shown in Fig. 9. The results are captured using an oscilloscope during open-loop and closed-loop control.
Open loop results. Figures 10,11,12 and 13 show the experimental results when the suggested DC-DC boost topology operates at D = 0.4. Fig. 10a shows the gate-emitter switch voltage waveform with duty cycle 40%. Fig. 10b shows the input and output voltage waveforms of the proposed converter. It is observed that the output DC voltage at this duty cycle equal to about 107 V obtained from input voltage equal to 24 V, that represents 4.46 times of the input voltage. Also, the output voltage ripple is equal to 4 V that represents 3.7% from the output voltage. It can be noticed from Fig. 10c that the input current is continuous with average value equal to about 2.36 A. The voltages of the capacitors C 1 and C 2 are shown in Fig. 10d and e, respectively. The voltages across the capacitors C 1 and C 2 are equal with value 21 V across each capacitor, which validates Eq. (21). The experimental waveforms of voltages and currents for L 1 and L 2 are captured in Fig. 11a and b, respectively. It can be noticed that i L1 and i L2 are continuous signals. This ensures that the converter operates in CCM. The average current value passes through L 1 or L 2 is found to be 1 A that confirms Eq. (18). The voltage across L 1 or L 2 is almost equal to the input voltage (24 V) during the mode 1, and their values are-14 V during mode 2 that confirm the analysis. To present the voltage gain against the duty cycle, the waveforms of Fig. 13 are plotted for derived and experimental results. It can be observed that the experimental and the theoretical curves have a good convergence. However, the slight variations between the theoretical and experimental results are due to the influence of parasitic elements. www.nature.com/scientificreports/ The converter efficiency against the output power at different values of the input voltage and at D = 0.4 is given in Fig. 14. The maximum measured efficiency at V in = 24 V and D = 0.4 is 92.6% and increases to 93.7% if the input voltage increases to 48 V. Also, it can be seen that the efficiency is enhanced with raising the input voltage. Furthermore, the measured efficiency at V in = 24 V and output power P o = 52 W is 91.2%. In this case, the total power losses equal 5 W that represents 9.6% from the output power. Also, Fig. 14 shows the theoretical efficiency curve at V in = 24 V that calculated from Eq. (66). The great convergence between the theoretical and measured efficiency curves proves the validity of the analysis. Table 2 shows the measured efficiency of the suggested converter and other similar works at the same output power, P o = 52 W. It is clear from Table 2 that the suggested converter has the highest efficiency compared to the other related topologies. Figure 15a illustrates the power losses division and the ratio of power losses for each component from the total power losses. The switch loss, the inductors losses, the capacitors losses, and the diodes losses represents 4%, 19%, 29%, and 48% of the total power losses, respectively. Figure 15b illustrates the efficiency pie chart at this experimental case. Hence, the converter efficiency can be enhanced by choosing low voltage/current rating of its components and the production of final converter fabrication.

Closed loop results.
The experimental prototype is also examined during a closed loop control. A schematic diagram of the circuit that is utilized to control the output voltage of the proposed converter is shown in Fig. 16. A PI controller is applied to regulate the output voltage. The parameters of the PI controller are K P = 100 and K I = 200. Figure 17 shows the output voltage response with changing the reference voltage (V ref ) at input dc voltage equal to 24 V and a full load value. A step change in the reference voltage from 125 to 105 V (decrease) and from

Discussion
In this part, a comparison between the two-cell proposed converter and other recent boost topologies is presented. Table 3 shows the comparison results according to the number of components, ideal voltage gain, and maximum voltage stresses through the main switch, output diode, and the output capacitors. The waveforms, which summarize the comparison, are plotted as shown in Figs. 20, 21 and 22. Figure 20 illustrates the variation of voltage gain when the duty cycle is varied, the proposed converter has the highest voltage gain for D ≤ 0.5. For D > 0.5, the converter in 29 has the highest voltage gain value. However, the proposed topology has a total number of components of 10 components, but the converter in 29 has 16 components which increases the cost and complexity of the system and decreases the efficiency. Also, the proposed converter has higher voltage gain for duty cycle varies from 0.5 to 0.67 than converters in [31][32][33] , and the conventional one. The normalized maximum switch voltage stress for each converter is recorded in Table 3 and shown in Fig. 21. Converter in 31 has the highest normalized switch voltage stress, while converter in 29 has the lowest normalized voltage stress, and approximately constant for all voltage gain values. The introduced converter has modest normalized voltage stress across the main switch. The normalized maximum output diode voltage stress for each converter is documented in Table 3 and shown in Fig. 22. The suggested converter has the lower normalized output diode voltage stress except the converter in 32 that has the lowest value. However, the converter in 32 has total number of components of 14 components which greater than the proposed converter that decreases the efficiency and increases the cost and the volume of the converter. From this comparative analysis, it is proved that the suggested converter has significant features in comparison to the modern topologies.

Conclusion
A new design of compact circuit that converts a low-level dc voltage to a high-level dc voltage has been proposed in this paper. It has a single switch and fewer passive components compared with recent boost converters. The new converter gets a high voltage gain at modest duty cycle, low switching losses, good efficiency, and it can be extended to get higher voltage gains by increasing the cascading additional cells. The suggested converter has been examined during open and closed loop process, and ensures a good control performance under reference voltage, input voltage, and load changes. Experimental results under different operating situations prove the usefulness of the new converter. In addition, the comparison between the new two-cell boost converter and         www.nature.com/scientificreports/

Data availability
All data generated or analyzed during this study are included in this published article.  www.nature.com/scientificreports/